June 22–26, 2014
Leipzig, Germany

Presentation Details

Name: Integration for Efficiency – How SoC Designs Can Reduce Data Center Power
Time: Thursday, June 26, 2014
11:30 am - 12:00 pm
Room:   Hall 3
CCL - Congress Center Leipzig
Speaker:   David Donofrio, LBNL
Abstract:   As power continues to be a driving force in supercomputer design we see that future systems will begin to rely on greater parallelism to achieve performance. Clock frequencies and single threaded performance continue to stagnate as vendors are unable to push per-socket power consumption. To continue to scale performance and increase energy efficiency vendors will begin to create heterogeneous SoC’s that present a radical alternative to conventional systems. Many of these designs borrow technologies and techniques from the cost and power sensitive design requirements found in the embedded world. For example, current multi-core chips have networks that are relatively simple and allow for all-to-all communication on chip. However, as core counts continue to increase, we will see more complex network on chip architectures begin to emerge. These on-chip networks will connect many components in a heterogeneous system that includes multiple core types, integrated NICs and stacked memory. This presentation will explore novel new architectures and design techniques for producing energy optimized processors. In addition, we will discuss a powerful new tool, OpenSoC Fabric, that allows for the design and exploration of novel new NoC topologies by generating both software models and hardware designs.