June 22–26, 2014
Leipzig, Germany

Presentation Details

Name: (02a) Modeling Power Usage of HPC Systems by RAPL Interface
Time: Thursday, June 26, 2014
10:30 am - 11:00 am
Room:   Hall 4
CCL - Congress Center Leipzig
Breaks:10:30 am - 11:00 am Coffee Break
07:30 am - 10:30 am Welcome Coffee
Presenter:   Thang Cao, University of Tokyo
Abstract:   Energy efficiency has become an indispensable criterion in designing and implementing HPC systems. To improve energy efficiency and to ensure that the operating peak power does not exceed predetermined power constraint, power usage of HPC systems should be monitored in fine temporal and spatial granularity. Though fine-grain power measurement mechanisms are already equipped in some commercial CPUs, it is not enough since the requirement is to monitor real-time power usage of each node or an entire system. This study presents a method to estimate power usage of HPC systems using Intel RAPL interface. Evaluation is conducted on an HPC cluster system with HPCC and NPB benchmarks. The results reveal that the method can estimate the system power with high accuracy.

Thang Cao, University of Tokyo; Masaaki Kondo, University of Tokyo; Yasutaka Wada, University of Electro-Communications; Hiroki Honda, University of Electro-Communications