June 22–26, 2014
Leipzig, Germany

Presentation Details

Name: FLOPs & Bandwidth, Are We Measuring the Right Metrics?
Time: Monday, June 23, 2014
05:40 pm - 06:00 pm
Room:   Hall 2
CCL - Congress Center Leipzig
Speaker:   Ian Karlin, LLNL
Abstract:   As computers have evolved, the performance bottleneck of HPC applications has changed. For implicit codes FLOPs were the first performance bottleneck, while more recently memory bandwidth has limited performance. However, many codes use other methods to solve PDEs and for energy transport. These methods, such as monte carlo and explicit hydrodynamics have performance bottlenecks that are different than linear algebra based applications. In this talk I present data showing the many machine design vectors we need to balance as we co-design general purpose exascale HPC systems. I show that latency to memory needs to be more strongly considered in system design and that the balance of compute capabilities in today's HPC microprocessors make it impossible for many modern applications to be limited by floating-point capability even if the bandwidth constraints on modern systems were solved.